The present invention relates to integrated circuits and semiconductor device fabrication and, more specifically, to structures for an on-chip capacitor and methods of forming an on-chip capacitor.
Device structures may be fabricated on a substrate by front-end-of-line (FEOL) processing and an interconnect structure fabricated by back-end-of-line (BEOL) processing may be used to electrically couple the FEOL device structures. The metallization levels of a BEOL interconnect structure may be formed using a damascene process. In a dual damascene process, via openings and trenches are formed and simultaneously filled with metal to create a metallization level. In a single-damascene process, the via openings and trenches are separately formed and filled with metal.
On-chip capacitors are components of an integrated circuit that are used for a variety of purposes, such as bypass and capacitive matching as well as coupling and decoupling. On-chip capacitors may be formed in the BEOL interconnect structure. A vertical native capacitor (VNCAP) is constructed from fingers of metal wires and vias that are formed in the BEOL interconnect structure.
Self-aligned patterning methods used in BEOL processing may utilize mandrels as sacrificial structures. Sidewall spacers, which have a thickness less than that permitted by the current ground rules for optical lithography, are formed on the vertical sidewalls of the mandrels. After selective removal of the mandrels, the sidewall spacers are used as an etch mask to etch an underlying hardmask and dielectric layer with, for example, a directional reactive ion etching (RIE). The features formed in the underlying dielectric layer will acquire the line pitch and width established by the sidewall spacers.
Cuts may be formed in mandrels with a cut mask and etching in order to section the mandrels. The cuts define gaps between mandrel tips that are subsequently used to form adjacent wires that are spaced apart at their tips with a tip-to-tip spacing related to the dimensions of the gaps. The pattern of the cut mandrels is transferred to the hardmask used to pattern the dielectric layer. Cuts may also be formed in the hardmask itself and filled by spacer material when sidewall spacers are formed on the mandrels. These cuts are also transferred to the hardmask and are eventually reflected in the patterned dielectric layer.
Improved structures for an on-chip capacitor and methods of forming an on-chip capacitor are needed.